`timescale 1ns/1ns module edge_detect( input clk, input rst_n, input a, output reg rise, output reg down ); reg ar ; always @(posedge clk or negedge rst_n) if(!rst_n) ar <= 0 ; else ar <= a ; always @(posedge clk or negedge rst_n) if(!rst_n) rise <= 0; else if (a && ~ar) ...