`timescale 1ns/1ns module comparator_4(input [3:0] A , input [3:0] B , output wire Y2, //A>B output wire Y1, //A = B output wire Y0); //A<B reg Y1r,Y0r,Y2r; wire [2:0] r1,r2,r3,r4; function [2:0] comp; input a; input b; begin comp[1] = a&b | ~a&~b; comp[0] = ~a & b; co...