`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input data, input data_valid, output reg match ); reg [1:0] q_current; reg [1:0] q_next; parameter IDLE = 0, S1 = 1, S2 = 2, S3 = 3; always@(posedge clk or negedge rst_n) if(!rst_n)begin q_current <= 2'b0; q...