`timescale 1ns/1ns module data_cal( input clk, input rst, input [15:0]d, input [1:0]sel, output reg [4:0]out, output reg validout ); //*************code***********// reg [15:0]datain; always@(posedge clk or negedge rst) if(!rst) datain <= 16'd0; else if(sel == 2'd0) datain <= d; alw...