题解 | #根据RTL图编写Verilog程序#

`timescale 1ns/1ns

module RTL(
	input clk,
	input rst_n,
	input data_in,
	output reg data_out
	);
reg    data_in_reg;
wire   data_in_pos;
always @(posedge clk or negedge rst_n) 
begin
    if(!rst_n)
        begin
            data_in_reg <= 0;
        end
    else 
        begin
            data_in_reg <= data_in;
        end
end
assign data_in_pos = !data_in_reg && data_in;

always @(posedge clk or negedge rst_n) 
begin
    if(!rst_n)
        begin
            data_out <= 0;
        end
    else 
        begin
            data_out <= data_in_pos;
        end
end

endmodule

时序图流程是，给输入data_in 打一拍得到data_in_reg。然后用wire型得到data_in的上升沿。这是个组合逻辑。所以必须使用assign赋值来写。最后将data_in_pos打一拍得到输出data_out。