题解 | 多bit MUX同步器

这题咋在跨时钟FIFO之后。。。

为了保险起见数据和使能都打两拍吧~

`timescale 1ns/1ns

module mux(
	input 				clk_a	, 
	input 				clk_b	,   
	input 				arstn	,
	input				brstn   ,
	input		[3:0]	data_in	,
	input               data_en ,

	output reg  [3:0] 	dataout
);

reg [3:0]	data_reg;
reg 		data_en_reg;

    always @(posedge clk_a or negedge arstn)           
        begin                                        
            if(!arstn)                               
                data_reg <= 4'd0;                                   
            else if (data_en)                             
                data_reg <= data_in;                                                                     
        end


    always @(posedge clk_a or negedge arstn)           
        begin                                        
            if(!arstn)                               
                data_en_reg <= 1'b0;                                   
            else
                data_en_reg <= data_en;                                                                     
        end		


reg 		data_en_pat1,data_en_pat2;
reg [3:0]   data_pat1,data_pat2;
    always @(posedge clk_b or negedge brstn)           
        begin                                        
            if(!brstn) begin
                data_en_pat1 <= 1'b0;
                data_en_pat2 <= 1'b0;       
            end                                             
            else begin
                data_en_pat1 <= data_en_reg;
                data_en_pat2 <= data_en_pat1;      
            end                                                                                                
        end

    always @(posedge clk_b or negedge brstn)           
        begin                                        
            if(!brstn) begin
                data_pat1 <= 1'b0;
                data_pat2 <= 1'b0;     
            end                                             
            else begin
                data_pat1 <= data_reg;
                data_pat2 <= data_pat1;     
            end                                                                                                
        end

    always @(posedge clk_b or negedge brstn)           
        begin                                        
            if(!brstn) begin
                dataout <= 4'd0;       
            end                                             
            else if (data_en_pat2) begin
                dataout <= data_pat2;      
            end                                                                                                
        end
                                              
endmodule