题解 | #多bit MUX同步器#

`timescale 1ns/1ns

module mux(
	input 				clk_a	, 
	input 				clk_b	,   
	input 				arstn	,
	input				brstn   ,
	input		[3:0]	data_in	,
	input               data_en ,

	output reg  [3:0] 	dataout
);

reg en_temp,en_b,data_en_a;
reg [3:0] data_reg;

always@(posedge clk_a or negedge arstn)
	if(!arstn)
		data_reg<=0;
	else
		//if(~data_en)//其实可以加入这句，避免在en是输入变化
			data_reg<=data_in;

always@(posedge clk_a or negedge arstn) begin
    if(~arstn)
        data_en_a <= 0;
    else
        data_en_a <= data_en;
end

always@(posedge clk_b or negedge brstn)
	if(!brstn)
		{en_temp,en_b}<=0;
	else
		{en_temp,en_b}<={data_en_a,en_temp};

always@(posedge clk_b or negedge brstn)
	if(!brstn)
		dataout<=0;
	else
		if(en_b)
			dataout<=data_reg;

endmodule