题解 | #脉冲同步器（快到慢）#

`timescale 100ps/100ps

module pulse_detect(
	input 				clka	, 
	input 				clkb	,   
	input 				rst_n		,
	input				sig_a		,

	output  		 	sig_b
);
    
reg data_fast_reg;
reg data_fast_reg_slow_1;
reg data_fast_reg_slow_2;
reg data_fast_reg_slow_3;

always @(posedge clka or negedge rst_n)begin
	if(rst_n == 1'b0)
		data_fast_reg <= 0;
	else if(sig_a == 1'b1)
		data_fast_reg <= ~data_fast_reg;
	else 
		data_fast_reg <= data_fast_reg;
end

always @(posedge clkb or negedge rst_n)begin
	if(rst_n == 1'b0)begin
		data_fast_reg_slow_1 <= 0;
		data_fast_reg_slow_2 <= 0;
		data_fast_reg_slow_3 <= 0;
	end
	else begin
		data_fast_reg_slow_1 <= data_fast_reg;
		data_fast_reg_slow_2 <= data_fast_reg_slow_1;
		data_fast_reg_slow_3 <= data_fast_reg_slow_2;
	end
end	

assign sig_b = data_fast_reg_slow_2 ^ data_fast_reg_slow_3;






endmodule