题解 | #状态机与时钟分频#

`timescale 1ns/1ns

module huawei7(
	input wire clk  ,
	input wire rst  ,
	output reg clk_out
);
parameter s0 = 0,s1 = 1;
reg state;

reg [1:0] fsm_cnt;

always @(posedge clk or negedge rst)begin
	if(rst  == 1'b0) begin
		state <= s0;
		fsm_cnt <= 0;
	end
	else begin
		case(state)
			s0 : begin
				fsm_cnt <= 0;
				state <= s1;
			end
			s1 : begin
				fsm_cnt <= fsm_cnt + 1;
				if(fsm_cnt >= 2)begin
					state <= s0;
					fsm_cnt <= 0;
				end
			end
		endcase
	end
end

always @(posedge clk or negedge rst)begin
	if(rst == 1'b0)
		clk_out <= 0;
	else if(state == s0)
		clk_out <= 1;
	else
		clk_out <= 0;
end



endmodule