题解 | #移位运算与乘法#

`timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant,
output reg [10:0]out
);
//*************code***********//
reg [1:0] cnt;
reg [7:0] d_0;



always @(posedge clk or negedge rst) begin

    if (!rst) begin
        cnt <= 0;
    end
    else  cnt <= cnt + 1;
end

always @(posedge clk or negedge rst) begin

    if (!rst) begin 
        input_grant <= 0;
        d_0 <= 0;
    end
    else if(cnt == 0) begin
        input_grant <= 1;
        d_0 <= d;
    end
    else input_grant <= 0;
end

always@(posedge clk or negedge rst)
    if(rst == 1'b0)
        out <= 11'd0;
    else case (cnt)
        2'd0 : out <= d;
        2'd1 : out <= (d_0<<2)-d_0;
        2'd2 : out <= (d_0<<3)-d_0;
        2'd3 : out <= (d_0<<3);
        default : out <= 11'd0;
    endcase

//*************code***********//
endmodule

能优化的地方就是2位的cnt 一直加1即可完成循环