题解 | #非整数倍数据位宽转换8to12#

`timescale 1ns/1ns

module width_8to12(
	input 			 clk 		,   
	input 			rst_n		,
	input			valid_in	,
	input	[7:0]	data_in	,
 
 	output  reg		   valid_out,
	output  reg [11:0] data_out
);
//本题中的波形图给的data_lock不是data_in
//实际上已经提示通过缓存来答题
reg [7:0] data_lock;
reg [1:0] data_cnt;

always@(posedge clk or negedge rst_n)begin
  if(!rst_n)
    data_cnt <= 1'b0;
  else if(valid_in)begin
    if(data_cnt == 2'b10)
	  data_cnt <= 1'b0;
	else
	  data_cnt <= data_cnt + 1'b1;
  end
  else
    data_cnt <= data_cnt;
end

always@(posedge clk or negedge rst_n)begin
  if(!rst_n)
    data_lock <= 1'b0;
  else if(valid_in)
    data_lock <= data_in;
  else
    data_lock <= data_lock;
end

always@(posedge clk or negedge rst_n)begin
  if(!rst_n)begin
    valid_out <= 1'b0;
	data_out  <= 1'b0;  
  end
  else if(valid_in)begin
    case(data_cnt)
	  2'b01:begin
	    valid_out <= 1'b1;
		data_out <= {data_lock,data_in[7:4]};
	  end
      2'b10:begin
		valid_out <= 1'b1;
		data_out  <= {data_lock[3:0],data_in};
	  end
	  default:begin
		valid_out <= 1'b0;
		data_out <= data_out;
	  end
	endcase
  end
  else begin
    valid_out <= 1'b0;
	data_out <= data_out;
  end
end



endmodule