题解 | #多bit MUX同步器#

`timescale 1ns/1ns

module mux(
	input 				clk_a	, 
	input 				clk_b	,   
	input 				arstn	,
	input				brstn   ,
	input		[3:0]	data_in	,
	input               data_en ,

	output reg  [3:0] 	dataout
);

reg [3:0] ram1;

reg data_en1;
reg data_en2;
reg data_en3;

always @(posedge clk_a or negedge arstn)begin
	if(!arstn)begin
		ram1 <= 4'b0000;
	end
	else begin
		if(data_en1)begin
			ram1 <= data_in;
		end
		else begin
			ram1 <= ram1;
		end
	end
end

always @(posedge clk_a or negedge arstn)begin
	if(!arstn)begin
		data_en1 <= 1'b0;
	end
	else begin
		data_en1 <= data_en;
	end
end

always @(posedge clk_b or negedge brstn)begin
	if(!brstn)begin
		data_en2 <= 1'b0;
		data_en3 <= 1'b0;
	end
	else begin
		data_en2 <= data_en1;
		data_en3 <= data_en2;
	end
end

always @(posedge clk_b or negedge brstn)begin
	if(!brstn)begin
		dataout <= 4'b0000;
	end
	else begin
		if(data_en3)begin
			dataout <= ram1;
		end
		else begin
			dataout <= dataout;
		end
	end
end

endmodule