题解 | #含有无关项的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

reg [8:0] a_tmp;

always@(posedge clk, negedge rst_n)begin
	if(!rst_n)begin
		a_tmp <= 9'd0;
		match <= 1'b0;
	end
	else begin
		a_tmp <= {a_tmp[7:0], a};
		match <= (a_tmp[8:6] == 3'b011 && a_tmp[2:0] == 3'b110);
	end
end
  
endmodule