题解 | #无占空比要去的奇数分频#

`timescale 1ns/1ns

module odd_div (    
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out5
);
//*************code***********//

reg [2:0] cnt_p, cnt_n;
always@(posedge clk_in, negedge rst) begin
    if(!rst) begin
        cnt_p <= 3'd0;
    end
    else begin
        if(cnt_p == 3'd5) cnt_p <= 3'd1;
        else cnt_p <= cnt_p + 3'd1;
    end
end

assign clk_out5 = rst?(cnt_p > 3'd0 && cnt_p < 3'd3):1'b0;

//*************code***********//
endmodule