题解 | #使用子模块实现三输入数的大小比较#

`timescale 1ns/1ns
module main_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	input [7:0]c,
	
	output reg [7:0]d
);
wire [7:0] min1, min2;
compare ab(.clk(clk), .rst_n(rst_n), .a(a), .b(b), .c(min1));
compare bc(.clk(clk), .rst_n(rst_n), .a(b), .b(c), .c(min2));
always @ (posedge clk or negedge rst_n)
	begin 
		if (!rst_n)
			d <= 0;
		else
			d <= (min1>min2)? min2:min1;
	end


endmodule 
module compare(input clk, input rst_n, input [7:0]a, input [7:0]b, output reg [7:0] c);
always @ (posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			begin
				c <= 0;
			end
		else
			c <= (a>b)? b:a;
	end
endmodule