题解 | #移位运算与乘法#

`timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant,
output reg [10:0]out
);
//*************code***********//
reg [1:0] flow;
reg [7:0] data_d;
always@(posedge clk or negedge rst)
begin
    if(!rst)
        flow<=2'd0;
    else if (flow == 2'd3)
        flow <= 2'd0;
    else 
        flow <= flow +1'd1;
end

always@(posedge clk or negedge rst)
begin
    if(!rst)
        input_grant <= 1'd0;
    else if(flow==0)
        input_grant <= 1'b1;
    else 
        input_grant <= 1'b0;
end

always @ (posedge clk or negedge rst)
begin
        if(!rst)
            data_d<=0;
        else if(flow==0)
            data_d <= d;
end
always @(posedge clk or negedge rst)
begin
        if(!rst)
            out <= 11'd0;
        else 
        begin
                case(flow)
                    2'd0:out <= d;
                    2'd1:out <= (data_d<<1)+data_d;
                    2'd2:out <= (data_d<<1)+(data_d<<2)+data_d;
                    2'd3:out <= data_d<<3;
                endcase
        end
end

//*************code***********//
endmodule