题解 | #根据状态转移表实现时序电路#

`timescale 1ns/1ns

module seq_circuit(
      input                A   ,
      input                clk ,
      input                rst_n,
 
      output   wire        Y   
);
    reg [1:0]cur_state;
    reg [1:0]nex_state;
    reg y_reg=0;

    always@(posedge clk or negedge rst_n)begin
        if(!rst_n)begin
            cur_state<=2'b00;
            nex_state<=2'b00;
        end
        else begin
            cur_state<=nex_state;
        end
    end

    always@(*)begin
        case(cur_state)
        2'b00:nex_state=(!A)?2'b01:2'b11;
        2'b01 : nex_state = (A == 1'b1) ? 2'b00 : 2'b10;
        2'b10 : nex_state = (A == 1'b1) ? 2'b01 : 2'b11;
        2'b11 : nex_state = (A == 1'b1) ? 2'b10 : 2'b00;
        default : nex_state = 2'b00;
        endcase
    end

    assign Y=(cur_state==2'b11)?1:0;
endmodule

两段式书写