题解 | #输入序列连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

parameter	[3:0]	IDLE = 4'd8,
					GET_0 = 4'd0,
					GET_01 = 4'd1,
					GET_011 = 4'd2,
					GET_0111 = 4'd3,
					GET_01110 = 4'd4,
					GET_011100 = 4'd5,
					GET_0111000 = 4'd6,
					GET_01110001 = 4'd7;

reg		[3:0]	c_state, n_state;

always@(posedge clk or negedge rst_n)
	if(!rst_n)
		c_state <= IDLE;
	else
		c_state <= n_state;

always@(posedge clk or negedge rst_n)
	if(!rst_n)
		match <= 1'b0;
	else if(c_state == GET_01110001)
		match <= 1'b1;
	else
		match <= 1'b0;

always@(*)
		case(c_state)
		IDLE		:
			if(!a)
				n_state <= GET_0;
			else
				n_state <= IDLE;
		GET_0		:
			if(!a)
				n_state <= GET_0;
			else if(a)
				n_state <= GET_01;
			else
				n_state <= IDLE;
		GET_01		:
			if(!a)
				n_state <= GET_0;
			else if(a)
				n_state <= GET_011;
			else
				n_state <= IDLE;
		GET_011		:
			if(!a)
				n_state <= GET_0;
			else if(a)
				n_state <= GET_0111;
			else
				n_state <= IDLE;
		GET_0111	:
			if(!a)
				n_state <= GET_01110;
			else if(a)
				n_state <= IDLE;
			else
				n_state <= IDLE;
		GET_01110	:
			if(!a)
				n_state <= GET_011100;
			else if(a)
				n_state <= GET_01;
			else
				n_state <= IDLE;
		GET_011100	:
			if(!a)
				n_state <= GET_0111000;
			else if(a)
				n_state <= GET_01;
			else
				n_state <= IDLE;
		GET_0111000	:
			if(!a)
				n_state <= GET_0;
			else if(a)
				n_state <= GET_01110001;
			else
				n_state <= IDLE;
		GET_01110001:
			if(!a)
				n_state <= GET_0;
			else if(a)
				n_state <= GET_011;
			else
				n_state <= IDLE;
		default		:
			n_state <= IDLE;
		endcase

endmodule