题解 | #多位信号#

`timescale 1ns/1ns

module top_module(
    input [2:0] in,
    output reg a,
    output reg b,
    output reg c
);

    always@(*)
        begin
            case(in)
                3'b000: c = in[0];
                3'b001: b = in[1];
                3'b010: a = in[2];
            endcase
        end
endmodule