题解 | #边沿检测#

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);

   reg a_r;
   always @(posedge clk or negedge rst_n) 
   begin
      if(~rst_n)
         a_r <= 1'b0;
      else
         a_r <= a;
   end

   always @(posedge clk, negedge rst_n)
   begin
      if(~rst_n) begin
         rise <= 1'b0;
         down <= 1'b0;
      end

      else if(a && (a^a_r)) begin
         rise <= 1'b1;
         down <= 1'b0;
      end

      else if(~a && (a^a_r)) begin
         rise <= 1'b0;
         down <= 1'b1;
      end
      else begin
         rise <= 1'b0;
         down <= 1'b0;
      end
   end
	
endmodule