题解 | #任意小数分频#

`timescale 1ns/1ns


module div_M_N(
 input  wire clk_in,
 input  wire rst,
 output wire clk_out
);
parameter M_N = 8'd87; 
parameter c89 = 8'd24; // 8/9时钟切换点
parameter div_e = 5'd8; //偶数周期
parameter div_o = 5'd9; //奇数周期

reg [6:0] cnt;
reg [3:0] cnt_8;
reg [3:0] cnt_9;
reg clk_87;
always@(posedge clk_in or negedge rst)begin
    if(!rst)begin
        cnt <= 0;
    end
    else begin
        cnt <= (cnt == M_N -1 ) ? 0 : cnt + 1;
    end
end
always@(posedge clk_in or negedge rst)begin
    if(!rst)begin
        cnt_8 <= 0;
        cnt_9 <= 0;
    end
    else if(cnt <= c89-1)begin
        cnt_8 <= (cnt_8 == div_e - 1) ? 0 : cnt_8 + 1;
    end
    else if(cnt > c89-1)begin
        cnt_9 <= (cnt_9 == div_o - 1) ? 0 : cnt_9 + 1;
    end
end
always@(posedge clk_in or negedge rst)begin
    if(!rst)begin
        clk_87 <= 0;
    end
    else if(cnt <= c89-1)begin
        clk_87 <= (cnt_8 == 4'd0 || cnt_8 == div_e/2) ? ~clk_87 : clk_87;
    end
    else if(cnt > c89-1)begin
        clk_87 <= (cnt_9 == 4'd0 || cnt_9 == (div_o-1)/2) ? ~clk_87 : clk_87;
    end
end
assign clk_out = clk_87;
endmodule