题解 | #不重叠序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);

	parameter	s1=3'd1,s2=3'd2,s3=3'd3,s4=3'd4,s5=3'd5,s6=3'd6,wa=3'd7;
	reg [2:0] c_state,n_state,cnt;

	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			cnt <= 3'd1;
		end
		else if(cnt == 3'd6) begin
			cnt <= 3'd1;
		end
		else begin
			cnt <= cnt + 1'b1;
		end
	end

	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			c_state <= s1;
			n_state <= s1;
		end
		else begin
			c_state <= n_state;
		end
	end

	always @(*) begin
		case(c_state)
			s1 : n_state = (data==1'b0) ? s2 : wa;
			s2 : n_state = (data==1'b1) ? s3 : wa;
			s3 : n_state = (data==1'b1) ? s4 : wa;
			s4 : n_state = (data==1'b1) ? s5 : wa;
			s5 : n_state = (data==1'b0) ? s6 : wa;
			s6 : n_state = (data==1'b0) ? s1 : wa;
			wa : n_state = (cnt == 3'd6) ? s1 : wa;
			default : n_state = s1;
		endcase
	end

	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			match <= 0;
			not_match <= 0;
		end
		else begin
			match <= c_state == s6 && cnt == 3'd6;
			not_match <= c_state == wa && cnt == 3'd6;
		end
	end

endmodule