题解 | #含有无关项的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);
//移位寄存器法
//reg [8:0]a1;
//always@(posedge clk or negedge rst_n)
//if(!rst_n)
//	a1 <= 9'b000000000;
//else
//	a1 <= {a1[7:0],a};
//always@(posedge clk or negedge rst_n)
//if(!rst_n)
//	match <= 0;
//else begin
//	casex(a1)
//		9'b011XXX110:match <= 1;
//		default:match <=0;
//	endcase
//end

//状态机法
reg[3:0]state;
reg[1:0]count;
parameter s0 = 4'd0;
parameter s1 = 4'd1;
parameter s2 = 4'd2;
parameter s3 = 4'd3;
parameter s4 = 4'd4;
parameter s5 = 4'd5;
parameter s6 = 4'd6;
parameter s7 = 4'd7;
parameter s8 = 4'd8;
parameter s9 = 4'd9;
always@(posedge clk or negedge rst_n)
if(!rst_n) begin
	state <= 4'd0;count <= 2'd0;
end
else begin
	case(state)
		s0:if(a == 0) state <= s1;
		    else state <= s0;
		s1:if(a == 1) state <= s2;
			else state <= s1;
		s2:if(a == 1) state <= s3;
			else state <= s2;
		s3:if(a == 1) state <= s4;
			else begin
				state <= s4;
				count <= count + 1;
			end
		s4:if(a == 0) state <= s5;
			else begin
				state <= s5;
				count <= count + 1;
			end
		s5:if(a == 0) state <= s6;
			else begin
				state <= s6;
				count <= count + 1;
			end
		s6:if(a == 1) state <= s7;
			else if(count == 3) state <= s4;
			else state <= s1;
		s7:if(a == 1) state <= s8;
			else state <= s1;
		s8:if(a == 0) state <= s9;
			else state <= s0;
		default:state <= s0;
	endcase
end
always@(posedge clk or negedge rst_n)
if(state == s9) match <= 1;
else match <=0;
endmodule