题解 | #状态机-非重叠的序列检测#

`timescale 1ns/1ns

module sequence_test1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
reg [5:0] state,next_state;
parameter IDLE=6'B000_001,
S1=6'B000_010,
S10=6'B000_100,
S101=6'B001_000,
S1011=6'B010_000,
S10111=6'B100_000;

always@(posedge clk or negedge rst)
if(!rst)
	state<=IDLE;
else 
	state<=next_state;

always@(*)
case(state)
IDLE: 	next_state=data?S1:IDLE;
S1:		next_state=data?S1:S10;
S10:	next_state=data?S101:IDLE;
S101:	next_state=data?S1011:IDLE;
S1011:	next_state=IDLE;

default:next_state=IDLE;
endcase

always@(posedge clk or negedge rst)
if(!rst)
	flag<=0;
else if(state==S1011 && data==1)
	flag<=1;
else
	flag<=0;

/* 
//moore型，多一个状态，晚一个周期
always@(*)
case(state)
IDLE: 	next_state=data?S1:IDLE;
S1:		next_state=data?S1:S10;
S10:	next_state=data?S101:IDLE;
S101:	next_state=data?S1011:IDLE;
S1011:	next_state=data?S10111:IDLE;
S10111: next_state=IDLE;

default:next_state=IDLE;
endcase

always@(posedge clk or negedge rst)
if(!rst)
	flag<=0;
else if(state==S10111)
	flag<=1;
else
	flag<=0;

	*/
//*************code***********//
endmodule