题解 | #异步复位同步释放#

`timescale 1ns/1ns

module ali16(
input clk,
input rst_n,
input d,
output reg dout
 );

 reg    rst0,rst1;

//*************code***********//


always@(posedge clk or negedge rst_n)
    if(!rst_n)
        begin
            rst1    <=  1'b0;
            rst0    <=  1'b0;
        end
    else
        begin
            rst0    <=  rst_n;
            rst1    <=  rst0;
        end

always@(posedge clk or negedge rst1)
    if(!rst1)
        dout    <=  1'b0;
    else 
        dout    <=  d;
//*************code***********//
endmodule