题解 | #位拆分与运算#

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output reg [4:0]out,
output reg validout
);
//*************code***********//

reg [15:0]temp;

always@(posedge clk or negedge rst)
if(!rst)
    begin out<=5'd0; validout<=1'b0;end
else
case(sel)
2'd0: begin temp<=d; out<=5'd0; validout<=1'b0;end
2'd1: begin out<=temp[3:0]+temp[7:4]; validout<=1'b1;end
2'd2: begin out<=temp[3:0]+temp[11:8]; validout<=1'b1;end
2'd3: begin out<=temp[3:0]+temp[15:12]; validout<=1'b1;end
default:begin out<=5'd0; validout<=1'b0;end
endcase


//*************code***********//
endmodule

注意题干：只有sel=0输入有效