题解 | #移位运算与乘法#

`timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant,
output reg [10:0]out
);
//*************code***********//
 
reg [4:0] state,next_state;
reg [7:0] temp;
 
parameter IDLE = 5'b00001,
        S1 = 5'b00010,
        S3 = 5'b00100,
        S7 = 5'b01000,
        S8 = 5'b10000;
 //第一段 跳转
always@(posedge clk or negedge rst)
if(!rst)
    state <= IDLE;
else
    state <= next_state;

 //第二段 条件
always@(*)
case(state)
IDLE: next_state = S1;
S1: next_state = S3;
S3: next_state = S7;
S7: next_state = S8;
S8: next_state = S1;
default: next_state = IDLE;
endcase

 //第三段-存一个temp
always@(state) //重点！！！！！！ 不能写*，不然d变了就会变
case(state)
S1: temp = d;
default: temp = temp;
endcase
 //第三段-输出out
always@(*)
case(state)
IDLE: out = 11'd0;
S1: out = temp;
S3: out = temp*3;
S7: out = temp*7;
S8: out = temp*8;
default: out = 11'd0;
endcase
//第三段-输出input_grant
always@(*)
case(state)
S1: input_grant = 1'b1;
default: input_grant = 1'b0;
endcase


//*************code***********//
endmodule