题解 | #状态机-重叠序列检测#

`timescale 1ns/1ns

module sequence_test2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
parameter	s0	=	4'b0001,
			s1	=	4'b0010,
			s2	= 	4'b0100,
			s3	=	4'b1000;

reg		[3:0]	cur_state,nxt_state;
reg		data_reg;
always@(posedge clk or negedge rst)
	if(!rst)
		data_reg	<=	0;
	else
		data_reg	<=	data;

always@(posedge clk or negedge rst)
	if(!rst)
		cur_state	<=	s0;
	else	
		cur_state	<=	nxt_state;

always@(*)
	if(!rst)		
		nxt_state	<=	s0;
	else	case(cur_state)
	s0:		nxt_state	<=	(data_reg)? s1:s0;
	s1:		nxt_state	<=	(data_reg)? s1:s2;
	s2:		nxt_state	<=	(data_reg)? s3:s0;
	s3:		nxt_state	<=	(data_reg)? s1:s2;
	default: nxt_state	<=	s0;
	endcase

always@(posedge clk or negedge rst)
	if(!rst)
		flag	<=	1'b0;
	else	if(cur_state == s3 && data_reg)
		flag	<=	1'b1;
	else	
		flag	<=	1'b0;
//*************code***********//
endmodule