题解 | #状态机-非重叠的序列检测#

`timescale 1ns/1ns

module sequence_test1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
parameter	s0	=	5'b00001,
			s1  =	5'b00010,
			s2	= 	5'b00100,
			s3	=	5'b01000,
			s4	=	5'b10000;
reg	[4:0]	cur_state,nxt_state;
reg	data_reg;
always@(posedge clk or negedge rst)
	if(!rst)
		data_reg	<=	1'b0;
	else	
		data_reg	<=	data;

always@(posedge clk or negedge rst)
	if(!rst)
		cur_state	<=	s0;
	else	
		cur_state	<=	nxt_state;

always@(*)
	if(!rst)
		nxt_state	<=	s0;
	else	case(cur_state)
	s0:begin
		nxt_state	<=	(data_reg)	? s1:s0;
	end
	s1:begin
		nxt_state	<=	(data_reg)	? s0:s2;
	end
	s2:begin
		nxt_state	<=	(data_reg)	? s3:s0;
	end
	s3:begin
		nxt_state	<=	(data_reg)	? s4:s2;
	end
	s4:begin
		nxt_state	<=	(data_reg)	? s0:s2;
	end
		default:	nxt_state	<=	s0;

	endcase


always@(*)
	if(!rst)
		flag	<=	1'b0;
	else	if(cur_state==s4 && data_reg)
		flag	<=	1'b1;
	else
		flag	<=	1'b0;

//*************code***********//
endmodule