题解 | #格雷码计数器#

`timescale 1ns/1ns

module gray_counter(
   input   clk,
   input   rst_n,

   output  reg [3:0] gray_out
);
    reg cnt_clk;
    reg [3:0] cnt;
    
    always @(posedge clk, negedge rst_n) begin
        if (~rst_n) begin
            cnt_clk <= 1'b1;
        end
        else begin
            cnt_clk <= cnt_clk + 1;
        end
    end

    always @(posedge cnt_clk, negedge rst_n) begin
        if (~rst_n) begin
            cnt <= 4'd0;
        end
        else begin
            cnt <= cnt + 1'd1;
        end
    end

    always @(*) begin
        gray_out = cnt ^ (cnt >> 1);
    end
endmodule

会二进制和格雷码互相转就行，题目没什么意义。