题解 | #多bit MUX同步器#

`timescale 1ns/1ns

module mux(
	input 				clk_a	, 
	input 				clk_b	,   
	input 				arstn	,
	input				brstn   ,
	input		[3:0]	data_in	,
	input               data_en ,

	output reg  [3:0] 	dataout
);

	reg data_en_reg0;
	always @(posedge clk_a or negedge arstn) begin
		if(!arstn) begin
			data_en_reg0 <= 0;
		end
		else begin
			data_en_reg0 <= data_en;
		end
	end

	reg data_en_reg1;
	reg data_en_reg2;
	always @(posedge clk_b or negedge brstn) begin
		if(!brstn) begin
			data_en_reg1 <= 0;
			data_en_reg2 <= 0;
		end
		else begin
			data_en_reg1 <= data_en_reg0;
			data_en_reg2 <= data_en_reg1;
		end
	end
	
	reg [3:0] data_reg;
	always @(posedge clk_a or negedge arstn) begin
		if(!arstn) begin
			data_reg <= 0;
		end
		else begin
			data_reg <= data_in;
		end
	end

	always@(posedge clk_b or brstn) begin
		if(!brstn) begin
			dataout <= 0;
		end
		else begin
			dataout <= (data_en_reg2)? data_reg : dataout;
		end
	end



endmodule