题解 | #可置位计数器#

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input set,
	input [3:0] set_num,
	output reg [3:0]number,
	output reg zero
	);

reg	[3:0]	number1;	

always@(posedge clk or negedge rst_n)
	if(!rst_n)
		number1	<=	4'd0;
	else	if(set)
		number1	<=	set_num;
	else
		number1	<=	number1	+ 1'b1;

always@(posedge clk or negedge rst_n)
	if(!rst_n)
		number	<=	4'd0;
	else
		number	<=	number1;

always@(posedge clk or negedge rst_n)	
	if(!rst_n)
		zero	<=	1'b0;
	else	if(number1 == 4'd0)
		zero	<=	1'b1;
	else	
		zero	<=	1'b0;
endmodule