题解 | #并串转换#

`timescale 1ns/1ns
module huawei5(
	input wire clk  ,
	input wire rst  ,
	input wire [3:0]d ,
	output wire valid_in ,
	output wire dout
	);

//*************code***********//
reg	[1:0]	cnt_bit;
reg	[3:0]	data;
reg			valid;

always@(posedge clk or negedge rst)
	if(!rst)
		begin
			cnt_bit	<=	1'b0;
			valid	<=	1'b0;
			data	<=	4'd0;
		end
	else	if(cnt_bit==2'd3)
		begin
			cnt_bit	<=	2'd0;
			valid	<=	1'b1;
			data	<=	d	;	
		end
	else	
		begin
			cnt_bit	<=	cnt_bit	+ 1'b1;
			valid	 <=	1'b0;
			data	<=	data;
		end

	assign	dout = data[3-cnt_bit];	
	assign	valid_in = valid;

endmodule