题解 | #自动贩售机1#

`timescale 1ns/1ns
module seller1(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire d3 ,
	
	output reg out1,
	output reg [1:0]out2
);
//*************code***********//

	// 状态是已经投入的钱，激励信号显示一次只会投0.5/1/1.5中的一个

	parameter [2:0] EMPTY = 0;
	parameter [2:0] M0_5  = 1;
	parameter [2:0] M1_0  = 2;
	parameter [2:0] M1_5  = 3;
	parameter [2:0] M2_0  = 4;
	parameter [2:0] M2_5  = 5;
	parameter [2:0] M3_0  = 6;

	reg [2:0] curr_state, next_state;

	// state transfer
	always @(negedge clk, negedge rst) begin
		if(!rst) begin
			curr_state <= EMPTY;
		end
		else begin
			curr_state <= next_state;
		end
	end

	// state switch
	always @(*) begin
		case(curr_state)
			EMPTY: next_state = (d1 & ~d2 & ~d3)? M0_5 :
								(~d1 & d2 & ~d3)? M1_0 :
								(~d1 & ~d2 & d3)? M2_0 : EMPTY;

			M0_5 : next_state = (d1 & ~d2 & ~d3)? M1_0 :
								(~d1 & d2 & ~d3)? M1_5 :
								(~d1 & ~d2 & d3)? M2_5 : 
								(~d1 & ~d2 & ~d3)?M0_5 : EMPTY;

			M1_0 : next_state = (d1 & ~d2 & ~d3)? M1_5 :
								(~d1 & d2 & ~d3)? M2_0 :
								(~d1 & ~d2 & d3)? M3_0 : 
								(~d1 & ~d2 & ~d3)?M1_0 : EMPTY;

			M1_5 : next_state = (d1 & ~d2 & ~d3)? M0_5 :
								(~d1 & d2 & ~d3)? M1_0 :
								(~d1 & ~d2 & d3)? M2_0 : EMPTY;

			M2_0 : next_state = (d1 & ~d2 & ~d3)? M0_5 :
								(~d1 & d2 & ~d3)? M1_0 :
								(~d1 & ~d2 & d3)? M2_0 : EMPTY;

			M2_5 : next_state = (d1 & ~d2 & ~d3)? M0_5 :
								(~d1 & d2 & ~d3)? M1_0 :
								(~d1 & ~d2 & d3)? M2_0 : EMPTY;

			M3_0 : next_state = (d1 & ~d2 & ~d3)? M0_5 :
								(~d1 & d2 & ~d3)? M1_0 :
								(~d1 & ~d2 & d3)? M2_0 : EMPTY;		

		endcase
	end

	// output logic
	always @(posedge clk, negedge rst) begin
		if(!rst) begin
			out1 <= 0;
			out2 <= 0;
		end
		else begin
			if(curr_state == M1_5) begin
				out1 <= 1;
				out2 <= 0;
			end
			else if(curr_state == M2_0) begin
				out1 <= 1;
				out2 <= 2'b01;
			end
			else if(curr_state == M2_5) begin
				out1 <= 1;
				out2 <= 2'b10;
			end
			else if(curr_state == M3_0) begin
				out1 <= 1;
				out2 <= 2'b11;
			end
			else begin
				out1 <= 0;
				out2 <= 0;
			end
		end
	end

//*************code***********//
endmodule