题解 | #根据RTL图编写Verilog程序#

`timescale 1ns/1ns

module RTL(
	input clk,
	input rst_n,
	input data_in,
	output reg data_out
	);

reg Q1;
always@(posedge clk or negedge rst_n) begin
	if(!rst_n)
		Q1 <= 'd0;
	else 
		Q1 <= data_in ;
end

always@(posedge clk or negedge rst_n) begin
	if(!rst_n)
		data_out <= 'd0;
	else 
		data_out <= D2 ;
end

assign D2 = data_in & (~Q1) ;

endmodule