题解 | #根据RTL图编写Verilog程序#
根据RTL图编写Verilog程序
https://www.nowcoder.com/practice/41a06522d8b242808c31a152bf948b5e
`timescale 1ns/1ns module RTL( input clk, input rst_n, input data_in, output reg data_out ); reg Q1; always@(posedge clk or negedge rst_n) begin if(!rst_n) Q1 <= 'd0; else Q1 <= data_in ; end always@(posedge clk or negedge rst_n) begin if(!rst_n) data_out <= 'd0; else data_out <= D2 ; end assign D2 = data_in & (~Q1) ; endmodule
，唯一的解就是行业好起来
