题解 | #四选一多路器#

`timescale 1ns/1ns
module mux4_1(
input [1:0]d1,d2,d3,d0,
input [1:0]sel,
output[1:0]mux_out
);
//*************code***********//
reg [1:0] mux_out1;
always@(*)
begin
    case(sel)
        2'b 00:begin
        mux_out1<=d3;
        end
        2'b 01:begin
        mux_out1<=d2;
        end
        2'b 10:begin
        mux_out1<=d1;
        end
        2'b 11:begin
        mux_out1<=d0;
        end
    endcase
end
assign mux_out=mux_out1;

//*************code***********//
endmodule