题解 | #状态机-重叠序列检测#

`timescale 1ns/1ns

module sequence_test2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,

	output reg flag
);
//*************code***********//

reg [3:0]state;
reg [3:0]data_reg;

parameter s1 = 4'b0001;
parameter s2 = 4'b0010;
parameter s3 = 4'b0100;
parameter s4 = 4'b1000;

always@(posedge clk or negedge rst)
    if (rst == 1'b0)
	    state <= s1;
	else
	    case(state)
		    s1 : if (data == 1'b0)
			        state <= s1;
				else 
				    state <= s2;
			s2 : if (data == 1'b0)
			        state <= s3;
				else 
				    state <= s2;
			s3 : if (data == 1'b0)
			        state <= s1;
				else
				    state <= s4;
			s4 : if (data == 1'b0)
			        state <= s2;
				else 
				    state <= s2;
			default : state <= s1;
		endcase
	    
always@(posedge clk or negedge rst)
    if (rst == 1'b0)
	    data_reg <= 4'b0;
	else 
	    data_reg <= {data_reg[3:0],data};

always@(posedge clk or negedge rst)
    if (rst == 1'b0)
	    flag <= 1'b0;
	else if (state == s2 && data_reg == 4'b1011)
	    flag <= 1'b1;
	else 
	    flag <= 1'b0;

//*************code***********//
endmodule