题解 | #Johnson Counter#

`timescale 1ns/1ns

module JC_counter(
   input                clk ,
   input                rst_n,
 
   output reg [3:0]     Q  
);
always @(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        Q <=4'b000 ;
    end
    else if(!Q[0]) begin
        Q <= {1'b1,Q[3:1]} ;
    end
    else begin
        Q <= {1'b0,Q[3:1]} ;
    end
end
endmodule