题解 | #根据状态转移写状态机-三段式#

`timescale 1ns/1ns

module fsm1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
reg		[2:0]		cur_state ;
reg		[2:0]		next_state ;
parameter S0 = 0 ,S1 = 1,S2 = 2,S3 = 3;
always @(posedge clk or negedge rst) begin
	if(!rst) begin
		cur_state <= S0 ;
	end
	else begin
		cur_state <= next_state ;
	end
end
always @(*) begin
	case(cur_state)
		S0 : begin
			if(data) begin
				next_state = S1;
			end
			else begin
				next_state = S0;
			end
		end
		S1: begin
			if(data) begin
				next_state = S2;
			end
			else begin
				next_state = S1;
			end
		end
		S2: begin
			if(data) begin
				next_state = S3;
			end
			else begin
				next_state = S2;
			end
		end
		S3: begin
			if(data) begin
				next_state = S0;
			end
			else begin
				next_state = S3;
			end
		end
	endcase
end
	always @(posedge clk or negedge rst ) begin
		if(!rst) begin
			flag <= 1'b0 ;
		end
		else if(cur_state == S3 && data) begin
			flag <= 1'b1 ;
		end
		else begin
			flag <= 1'b0 ;
		end
	end

//*************code***********//
endmodule