题解 | #占空比50%的奇数分频#

`timescale 1ns/1ns

module odo_div_or
   (
    input    wire  rst ,
    input    wire  clk_in,
    output   wire  clk_out7
    );

//*************code***********//
reg         [2:0]       cnt ;
reg                     clk_p ;
reg                     clk_n ;

always @(posedge clk_in or negedge rst) begin
    if(!rst) begin
        cnt <= 3'b0 ;
    end
    else if(cnt == 3'd6)begin
        cnt <= 3'b0;
    end
    else begin
        cnt <= cnt + 3'b1 ;
    end
end
always @(posedge clk_in or negedge rst) begin
    if(!rst) begin
        clk_p <= 1'b0 ;
    end
    else if(cnt == 3'd3)begin
        clk_p <= 1'b1;
    end
    else if(cnt == 3'd6)begin
        clk_p <= 1'b0 ;
    end
end
always @(negedge clk_in or negedge rst) begin
    if(!rst) begin
        clk_n <= 1'b0 ;
    end
    else if(cnt == 3'd3)begin
        clk_n <= 1'b1;
    end
    else if(cnt == 3'd6)begin
        clk_n <= 1'b0 ;
    end
end
assign clk_out7 = clk_p | clk_n ;
//*************code***********//
endmodule