题解 | #根据RTL图编写Verilog程序#

`timescale 1ns/1ns

module RTL(
	input 		clk,
	input 		rst_n,
	input 		data_in,
	output 		reg data_out
	);
reg   data_reg0;
wire  data_reg1;
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		data_reg0 <= 'b0;
	else 
		data_reg0 <= data_in;
end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		data_out <= 'b0;
	else 
		data_out<= data_reg1;
end

assign data_reg1 = data_in & (~data_reg0);
		
endmodule