题解 | #加减计数器#

`timescale 1ns/1ns

module count_module(
	input 				clk,
	input 				rst_n,
	input 				mode,
	output reg [3:0]	number,
	output reg 			zero
	);

reg[3:0] num;
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		zero<=1'b0;
	else if(num==4'd0)
		zero<=1'b1;
	else
		zero<=1'b0;
end

always@(posedge clk or negedge rst_n)begin
	 if (!rst_n)
			num <= 4'b0;
        else if(mode)
            begin
                if(num == 9)
                    num <= 0;
                else
                    num <= num + 1'd1;
            end
        else if(!mode)
            begin
                if(num == 0)
                    num <= 9;
                else
                    num <= num - 1'd1;
            end
        else num <= num;
end


always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		number<=4'd0;
	else
		number<=num;
end
endmodule