题解 | #位拆分与运算#

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output reg [4:0]out,
output reg validout
);
//*************code***********//
reg [15:0] valid_lock;

always @ (posedge clk or negedge rst) begin
   if (!rst)  begin valid_lock<=16'b0;  end
   else if (!sel)  begin valid_lock<=d;  end
end

always @ (posedge clk or negedge rst) begin
   if (!rst)  begin validout<=0;out<=0;end
   else begin case (sel)
            2'd0:begin validout<=0;out<=0  ; end
            2'd1:begin validout<=1;out<=valid_lock[3:0]+valid_lock[7:4]  ; end
            2'd2:begin validout<=1;out<=valid_lock[3:0]+valid_lock[11:8] ; end
            2'd3:begin validout<=1;out<=valid_lock[3:0]+valid_lock[15:12];end
             endcase
        end
end





//*************code***********//
endmodule