题解 | #使用子模块实现三输入数的大小比较#

`timescale 1ns/1ns
module main_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	input [7:0]c,
	
	output [7:0]d
);

wire [7:0] m,n;

compare compare1(
.clk(clk),
.rst_n(rst_n),
.data_a(a),
.data_b(b),
.data_c(m)
);

compare compare2(
.clk(clk),
.rst_n(rst_n),
.data_a(a),
.data_b(c),
.data_c(n)
);

compare compare3(
.clk(clk),
.rst_n(rst_n),
.data_a(m),
.data_b(n),
.data_c(d)
);

endmodule


module compare(
	input clk,
	input rst_n,
	input [7:0] data_a,data_b,
	output reg [7:0] data_c);

always @ (posedge clk or negedge rst_n )
  if (!rst_n)
     data_c <=0;
  else if (data_a<data_b)
     data_c <=data_a;
  else 
     data_c <=data_b;
endmodule