题解 | #占空比50%的奇数分频#

`timescale 1ns/1ns

module odo_div_or
   (
    input    wire  rst ,
    input    wire  clk_in,
    output   wire  clk_out7
    );

//*************占空比50%的奇数N分频(7分频) 半个周期为3.5个clk_in***********//

//关键是(N-1)/2和(N-1)翻转，上升沿和下降沿分别计数

reg[2:0] cnt;
reg clk_pos,clk_neg;


always@(posedge clk_in or negedge rst)begin
    if(!rst)
        cnt <=3'd0;
    else if(cnt==3'd6)
        cnt <=3'd0;
    else
        cnt <=cnt+1'b1;
end

always@(posedge clk_in or negedge rst)begin
    if(!rst)
        clk_pos  <= 0;
    else if(cnt== 3'd3 || cnt == 3'd6 )
        clk_pos  <= ~clk_pos;
    else
        clk_pos  <= clk_pos;
end

always@(negedge clk_in or negedge rst)begin
    if(!rst)
        clk_neg  <= 0;
    else if(cnt== 3'd3 || cnt == 3'd6 )
        clk_neg  <= ~clk_neg;
    else
        clk_neg  <= clk_neg;
end

assign clk_out7 = clk_pos|clk_neg;


endmodule