题解 | #对信号按位操作#

`timescale 1ns/1ns

module top_module( 
    input [4:0] in,
    output out_and,
    output out_or,
    output out_xor
);
assign out_and = & in;//注意对自身按位操作是这样的
assign out_or = | in;
assign out_xor = ^ in;
endmodule