题解 | #序列发生器#

module sequence_generator(
	input clk,
	input rst_n,
	output reg data
	);
reg [2:0] cnt;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
cnt<=3'd0;
end
else
begin
cnt<= cnt== 3'd5 ? 3'd0 :cnt+3'd1;
end
end
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
data<=0;
end
else 
begin
case (cnt)
3'd0: begin  data<=1'b0; end
3'd1: begin  data<=1'b0; end
3'd2: begin  data<=1'b1; end
3'd3: begin  data<=1'b0; end
3'd4: begin  data<=1'b1; end
3'd5: begin  data<=1'b1; end
endcase 
end
end
endmodule

`timescale 1ns/1ns

module textbench();
reg clk , rst;
wire data;
sequence_generator u0(
	.clk(clk),
	. rst_n(rst),
	. data(data)
	);
 always #5 clk=~clk;
 initial 
 begin
 rst=0;clk=1;
 #25 rst=1;
 #300;
 $finish;
 end
endmodule

仿真波形如下：