题解 | #根据RTL图编写Verilog程序#

`timescale 1ns/1ns

module RTL(
	input clk,
	input rst_n,
	input data_in,
	output reg data_out
	);
reg data,temp;

always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
data<=1'b0;
end
else
begin
data<=data_in;
end
end

always@(*)
begin
temp=data_in&~data;
end

always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
data_out<=1'b0;
end
else
begin
data_out<=temp;
end
end
endmodule