题解 | #整数倍数据位宽转换8to16#

module width_8to16(
	input 				   clk 		,   
	input 				   rst_n		,
	input				      valid_in	,
	input	   [7:0]		   data_in	,
 
 	output	reg			valid_out,
	output   reg [15:0]	data_out
);
reg [1:0] cnt,temp;
reg [15:0] out;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
cnt<=2'd0;
temp<=2'd0;
end
else
begin
if(valid_in)
begin
cnt<= cnt==2'd2 ? 2'd1 : cnt+2'd1;
end
else
begin
cnt<=cnt;
end
temp<=cnt;
end
end
always @(*)
begin
if(!rst_n)
begin
valid_out<=1'b0;
end
else
begin
valid_out<= (temp==2'd1 && cnt==2'd2);
end
end
    always @(posedge clk or negedge rst_n)
    begin
    if(!rst_n)
    begin
    out<=16'd0;
    end
    else if (valid_in)
    begin
    out<={out[7:0],data_in};
    end
    end
    always @(* )
    begin
    if(!rst_n)
    begin
       data_out<=16'd0;
    end
     else if (temp==2'd1 && cnt==2'd2)
    begin
    data_out<=out;
    end
    end
  

endmodule

`timescale 1ns/1ns
module testbench();
    reg rst,valid_in;
	reg clk=1;
 reg[7:0] data_in;
 wire valid_out;
 wire [15:0] data_out;
	 width_8to16 u0(
      .clk (clk),   
	  .rst_n(rst),
	 . valid_in(valid_in),
	.data_in(data_in),
 	.valid_out(valid_out),
     .data_out(data_out)
);
	always #5 clk = ~clk;  // Create clock with period=10 
  initial begin
  rst=0;valid_in=0;
 #10 rst=1;valid_in=1;data_in=8'ha0;
#10 data_in=8'ha1;
#10 data_in=8'hb0;
#10 valid_in=0;
#20 valid_in=1;data_in=8'hb1;
#10 valid_in=0;
#30
 $finish;
end  
    
endmodule

仿真波形如下：