题解 | #简易秒表#

module count_module(
	input clk,
	input rst_n,

    output reg [5:0]second,
    output reg [5:0]minute
	);
always @ (posedge clk or negedge rst_n )
begin
if(!rst_n)
begin
second<=6'd0;
end
else
begin
second<= second==6'd60 ? 6'd1: second+6'd1;
end
end	

always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
minute<=6'd0;
end
else
begin
if(second==6'd60)
begin
minute<= minute==6'd60 ? 6'd1: minute+6'd1;
end
else
begin
minute<= minute;
end
end
end
endmodule

`timescale 1ns/1ns
module testbench();
    reg rst;
	reg clk=1;
	wire[5:0] second,minute;
	 count_module u1(
	. clk(clk)  ,
	.rst_n(rst) ,
    .second(second),
    .minute(minute)
);
	always #5 clk = ~clk;  // Create clock with period=10 
  initial begin
  rst=0;
 #10 rst=1;
 #36620;
 $finish;
end  
    
endmodule

仿真图如下：